The present invention relates to a driving method for a plasma display panel (PDP), and more particularly, to a method of providing erase pulses with different voltage values so as to make the voltages of the remaining wall charges of the plurality of the display units during the reset period relatively the same, and to ensure that the plurality of display units are driven properly during the following address period and sustain period so that the probability of the erroneous discharging is decreased.
Recently, plasma display panels (PDP) are becoming the most commonly used large-sized displays due to their large, slender size and their irradiative characteristic. A PDP includes a plurality of display units positioned within a matrix. Each display unit includes one sustain electrode (The X electrode), one scanning electrode (the Y electrode), and one data electrode (the A electrode), for sealing an inert gas and each unit is driven with a fixed driving sequence by a driving circuit to allow the inert gas to repeatedly emit light. A proper driving sequence can be divided into the following periods: a) reset period, b) address period, and c) sustain period. A display panel of the PDP can equivalently be regarded as a capacitor. By charging the capacitor and applying the two ends (The X electrodes and the Y electrodes) of the capacitor with alternating current (AC) pulses, the gas atoms within the display units are able to repeatedly emit ultraviolet light. Then, the ultraviolet light of a specific wavelength is absorbed by the phosphors within the display unit to emit visible light.
It is necessary to provide the moderate driving waveforms and voltages during the sustain period of the driving sequence to allow the display units to emit visible light. Different driving voltages affect the operation of the display units, whereby the display units can be properly driven within the specific range of driving voltages. The PDP should be operated under an adequate sustain operating voltage range, whereby the larger the adequate sustain operating voltage range, the more efficient the plasma display panel.
Please refer to FIG. 1, FIG. 1 is a timing diagram of the driving sequence for a plasma display panel of a prior art. The driving circuit of the prior art applies a first soft erase pulse 62, with a time interval of 100 xcexcs, to the Y electrodes 18 of all the display units to reduce the remaining wall charges of the last sustain period. Then, the driving circuit applies a soft priming pulse 64 on all the X electrodes to re-generate the wall charges, followed by the a second soft erase pulse 66, with a time interval of 100 xcexcs, on all the Y electrodes 18 to again reduce the wall charges. In order to cope with the image information during the following sustain period, the wall charges generated by the address discharges that caused by the data electrodes (the A electrodes) and the scanning electrodes (the Y electrodes) need to be correctly inputted into the assigned display units. Then, applying repeated sustain pulses 68 on both the X electrodes 16 and the Y electrodes 18 allow the inert gas to emit light and images are displayed.
Since the first soft erase pulse 62 and the second soft erase pulse 66 are generated by the same driving circuit, both their voltages and their time constant of the rising slopes are equal. Also, the voltage of the sustain pulses 68 is equal to the peak voltage of the first soft erase pulse 62 and that of the second soft erase pulse 66, represented as Vs. However, the differences between the display units would lead to he images showed on the plasma panel flickeringly. It is the reason that the inability to make the voltages of the remaining wall charges in different display units relatively the same after the reset period.
It is an object of the present invention to provide a new driving method, which is simple and efficient to drive all display units, and to decrease the differences of the wall voltages in different display units so as that the remaining wall charges relatively the same after the reset period to solve the flickering problem of the PDP.
In accordance with the present invention, a driving method during the reset period of a PDP involves applying a first soft erase pulse on the first electrodes of the plurality of display units to reduce the wall charges of the plurality of the display units. Next, a soft priming pulse is applied on the second electrodes of the plurality of display units to reproduce the wall charges of the plurality of display units. Finally, a second soft erase pulse is applied on the first electrodes of the plurality of the display units to clear the wall charges of the plurality of the display units and decrease the differences of the wall voltages in different display units so as that of the remaining wall charges of the plurality of the display units relatively the same, due to the voltage of the second soft erase pulse being greater than that of the first soft erase pulse.
It is an advantage of the present invention that it provides different voltage levels for the first soft erase pulse and the second soft erase pulse to make the voltage levels of the remaining wall charges relatively the same during the reset period and reduce the flickering in the PDP.